1. Field of the Invention
This invention relates to processors. More specifically, this invention relates to processors that convert an x86 instructions into RISC-type operations for execution on a RISC-type core.
2. Description of the Related Art
Advanced microprocessors, such as P6-class x86 processors, are defined by a common set of features. These features include a superscalar architecture and performance, decoding of multiple x86 instructions per cycle and conversion of the multiple x86 instructions into RISC-like operations. The RISC-like operations are executed out-of-order in a RISC-type core that is decoupled from decoding. These advanced microprocessors support large instruction windows for reordering instructions and for reordering memory references.
The conversion or translation of CISC-like instructions into RISC-like instructions typically involves a mapping of many like-type instructions, for example many variations of an ADD instruction, into one or more generic instructions. Furthermore, a very large number of addressing modes of a particular instruction are converted into a register-to-register operation in combination with load and store operations accessing memory. Performance of a microprocessor that converts CISC-type instructions into RISC-type instructions for execution depends greatly on the number of RISC-type operations produced from a single CISC-type instruction.
Performance of an advanced superscalar microprocessor is also highly dependent upon decoding performance including decoding speed, the number of x86 instructions decoded in a single cycle, and branch prediction performance and handling. Instruction decoders in advanced superscalar microprocessors often include one or more decoding pathways in which x86 instructions are decoded by hardware logic translation and a separate decoding pathway which uses a ROM memory for fetching a RISC operation sequence that corresponds to an x86 instruction. Generally, x86 instructions that are translated by hardware logic are simple x86 instructions. The lookup ROM is used to decode more complex x86 instructions.
One problem with the usage of lookup ROM for decoding x86 instructions is that the process of accessing a microprogram control store is inherently slower and less efficient than hardwired translation of instructions.
A further problem arising with decoding of x86 instructions via lookup ROM is the very large number of different CISC-type instructions that are standard for an x86 processor. Since a substantial number of instructions are implemented, a large ROM circuit on the processor chip is necessary for converting the instructions to RISC-like operations. The large number of implemented instructions corresponds to an increased circuit complexity for deriving pointers to the ROM and applying the derived pointers to the ROM. This increased circuit complexity directly relates to an increased overhead that reduces instruction decoding throughput. A large lookup ROM increases the size of the processor integrated circuit and thereby reduces manufacturing yields of the circuits and increases production costs.
What is needed is an internal instruction format that facilitates translation of a very large number of CISC-type instructions into a small number of RISC-type operations. What is also needed is an internal instruction format that facilitates conversion of CISC-type instructions into a minimum number of RISC-type operations. What is further needed is an internal instruction format that permits more common CISC-type instructions to be converted using hardwired logic, as compared to conversion via lookup ROM.